1. Technical Field
The present invention relates to a data transfer circuit and a flat display device that can be applied to a liquid crystal display apparatus having a drive circuit formed integrally, for example, on an insulating substrate. According to the present invention, it is configured such that only an inverted output of a latch result of a first latch section or only a non-inverted output thereof is data-transferred to a second latch section, and that at least during a data transfer to the second latch section, a power supply voltage of the first latch section is raised, thereby enabling the simplification of a configuration relating to the data transfer, in a construction with TFTs and the like.
2. Background Art
Recently, in a liquid crystal display apparatus of a flat display device applicable to a portable terminal such as, for example, PDAs, portable telephones and the like, there has been provided an arrangement in which a drive circuit of a liquid crystal display panel is formed integrally on a glass substrate which is an insulating substrate constituting the liquid crystal panel.
Namely, FIG. 1 is a block diagram showing this type of a liquid crystal display apparatus. In this liquid crystal display apparatus 1, each pixel is formed with a liquid crystal cell 2, a polysilicon TFT (Thin Film Transistor) 3 as a switching element of this liquid crystal cell 2 and a hold capacitance which is not shown, and a display section 4 of a rectangular shape is formed by arranging each pixel in a matrix. In this liquid crystal display apparatus 1, by disposing a color filter to each pixel formed in the display section 4 as described above, pixels R, G, B in red, green and blue colors are repeated sequentially and cyclically in a horizontal direction, with 240 sets of red, green and blue color pixels R, G and B as one set, and pixels in the horizontal direction are formed so as to form the display section 4. In this liquid crystal display unit 1, gradation data R0-R5, G0-G5, B0-B5, each with 6 bits, for indicating the gradation of these red, green, blue color pixels R, G, B are inputted simultaneously and in parallel in the order of raster scan, and the unit is enabled to display a desired image by driving each pixel on the basis of this gradation data D1 (R0-R5, G0-G5, B0-B5).
In the liquid crystal display apparatus 1, signal lines SL and gate lines SG of the display section 4 are connected to a horizontal drive circuit 5 and a vertical drive circuit 6, respectively. The horizontal drive circuit 5 outputs a drive signal for pixels corresponding to each signal line SL on the basis of the gradation data D1, and the vertical drive circuit 6, in correspondence to an output of the drive signal to the signal line SL by this horizontal drive circuit 5, selects pixels per line unit in the display section 4 by controlling the gate lines SG. Thereby, in the liquid crystal display apparatus 1, a desired image is enabled so as to be displayed by driving each pixel in the display section 4 with these horizontal drive circuit 5 and vertical drive circuit 6.
More specifically, by selecting a plurality of reference voltages V0-V63 according to gradation data, the horizontal drive circuit 5, as described in Japanese Patent Application Publication No. 2000-242209, is enabled so as to perform a digital/analog conversion processing of the gradation data D1 and generate a drive signal. That is, in the horizontal drive circuit 5, by means of sampling latch circuits (SL) 8 that are provided corresponding to the disposition of pixels in the horizontal directions, by sequentially and cyclically sampling corresponding bits of R0-R5, G0-G5, B0-B5 of the gradation data D1, and by arranging together these gradation data D1 per line unit, they are outputted to reference voltage selectors 9 corresponding thereto. A reference voltage generating circuit 10 generates and outputs a plurality of reference voltages V0-V63 corresponding to each gradation of the gradation data D1. The reference voltage selector 9 selects the reference voltages V0-V63 outputted from this reference voltage generating circuit 10, based on the output data from each sampling latch circuit 8, and outputs a drive signal obtainable by a digital/analog conversion processing of corresponding gradation data D1. A buffer circuit 11 outputs this drive signal to a corresponding signal line SL.
FIG. 2 is a connection diagram showing a configuration for one bit portion of the sampling latch circuit 8 in the horizontal drive circuit 5 composed as described above. In the sampling latch circuit 8, after latch-holding gradation data D1 in a first latch section 21 at a timing corresponding to a position of a corresponding pixel in the horizontal direction, a latch result of the first latch section 21 is transferred and outputted to a second latch section 22 at a predetermined timing set in a vertical blanking period, thereby arranging the gradation data together per line unit and outputting it to the reference voltage selector 9. Here, with respect to active elements, such as a low temperature polysilicon TFT or the like which is formed on an insulating substrate for constructing this type of sampling latch circuit 8 or the like, there is a large dispersion in their characteristics. Therefore, in the sampling latch circuit 8, the circuit is configured to output the latch result to the second latch section 22 with a so-called bi-phase output by outputting an inverted output 1Lout(Inv) of the latch result as well as a non-inverted output 1Lout(Non-inv) thereof so as to ensure a stable and reliable data transfer of the latch result to be secured between the first latch section 21 and the second latch section 22.
That is, in the first latch section 21 in this sampling latch circuit 8, a CMOS inverter composed of a N-channel MOS (hereinafter referred to as a NMOS) and a P-channel MOS (hereinafter referred to as a PMOS), a gate and a drain being connected respectively in common therebetween, as well as a CMOS inverter composed of an NMOS transistor Q3 and a PMOS transistor Q4, and likewise, a gate and a drain being connected respectively in common therebetween, are provided in parallel between a positive side power supply line of power supply voltage VCC and a negative side power supply line of power supply voltage VSS. In the first latch section 21, an inverter output by means of the transistors Q1 and Q2 is inputted to an inverter composed of the transistors Q3 and Q4. Further, via a PMOS transistor Q5 operating at an inverted signal xSP of a sampling pulse SP, an inverter output by means of the transistors Q3 and Q4 is inputted to the inverter composed of the transistors Q1 and Q2, and still further, via a PMOS transistor Q6 operating at a sampling pulse SP, gradation data D1 is inputted to the inverter composed of the transistors Q1 and Q2.
Thereby, in the sampling latch circuit 8, a CMOS latch cell with a comparator configuration is formed with transistors Q1 to Q6, wherein, as shown in FIGS. 3(A) to 3(D), gradation data D1 is caused to be latched by the sampling pulse SP, and a timing of this latch is configured to be set according to the position of a corresponding pixel in the horizontal direction.
In the sampling latch circuit 8, an inverted output 1Lout(Inv) of a latch result by this first latch section 21 and a non-inverted output 1Lout(Non-inv) thereof are inputted to the second latch section 22, respectively, via transfer switches 25, 24. Here, this transfer switch 25, 24 turns to an ON-state at a timing OE1, for example, of a rise timing in a horizontal blanking period (FIG. 3(E)).
In the second latch section 22, a latch cell is formed with a CMOS inverter composed of an NMOS transistor Q7 and a PMOS transistor Q8, and a CMOS inverter composed of an NMOS transistor Q9 and a PMOS transistor Q10. An inverted output 1Lout(Inv) and a non-inverted output 1Lout(Non-inv) of the latch result inputted via the transfer switches 25, 24 are inputted to the CMOS inverter composed of the transistors Q7, Q8 and the CMOS inverter composed of the transistors Q9, Q10, respectively. Thereby, the sampling latch circuit 8 is configured to perform data transfer of a latch result of the first latch section 21 at a timing OE1 of the rise in the horizontal blanking period for latching in the second latch section 22 (FIG. 3.(F)), and to output the output 2Lout of the latch result of the second latch via an inverter 26. By way of example, in the second latch section 22, by setting a positive power supply and a negative power supply appropriately, a latch output may be outputted after level-shifting to be suitable for processing in the following reference voltage selector 9.
However, in the case of data transfer of the latch result and the like by use of the bi-phase as described above, there is a problem that its configuration becomes complicated in comparison with a data transfer by use of a single phase. If the construction relating to such data transfer can be simplified, an overall configuration can be simplified in accordance therewith, and a so-called narrow bezel can be realized in this type of display apparatus. Further, power consumption can be reduced.